A wide variety of memory devices are in common use. Common types of memory device are random access memory (“RAM”) devices, which are generally either static random access memory (“SRAM”) devices or dynamic random access memory (“DRAM”) devices. Either of these types of RAM devices can operate synchronously with a clock signal. For example, in a synchronous dynamic random access memory (“SDRAM”) device, command, address, and write data signals are applied to a synchronous dynamic random access memory (“SDRAM”) device and are registered on one or both transitions of a clock signal. In practice, the address signals are commonly divided into bank address signals, row address signals, and column address signals. These address signals are generally applied to the SDRAM device through an address bus. The row address signals are applied to the SDRAM device prior to applying the column address signals to the SDRAM device. The bank address signals are generally applied to the SDRAM device along with the row address signals, although they may alternatively be applied to the SDRAM device at other times.
The SDRAM device responds to the command signals and address signals by performing a memory access operations, such as by storing write data in the SDRAM or by coupling read data from the SDRAM. As mentioned above, the write data signals are normally registered in the SDRAM in synchronism with either the clock signal or a write data strobe signal that is derived from the clock signal. Similarly, read data signals are output from the SDRAM in synchronism with either the clock signal or a read data strobe signal that may also be derived from the clock signal.
The timing relationship between the address signals and the data signals vary as a function of the operating mode of the SDRAM device. A set of bank and row address signals and a set of column address signals may be required for each set of read data signals or write data signals. If the data signals are coupled to or from the SDRAM on each rising edge of the clock signal, then it will be necessary to apply one of the two sets of address signals to the SDRAM on both the rising and falling edge of the clock signal to provide maximum data bandwidth. However, the if data signals may be multiplexed so that half of the data signals are coupled to or from the SDRAM on a first rising edge of the clock signal and the other half of the data signals are coupled to or from the SDRAM on the next rising edge of the clock signal. In such case, the maximum data bandwidth can be achieved by applying one of the two sets of address signals to the SDRAM on only the adjacent rising edges of the clock signal. Other relationships between the timing of the data signals and the timing of the address signals can also be used.
The timing relationship between the data signals and the address signals is also affected by whether the SDRAM device is operating in a “burst” mode. In a burst mode, a set of bank/row address signals and a set of column address signals define a starting address for a read or write operation. Data are then coupled to or from the SDRAM device in synchronism with a number of cycles of the clock signal. For example, in a “burst 4” mode, 4 sets of write data are coupled to or read data are coupled from an SDRAM device responsive to the set of bank/row address signals and a set of column address signals. If data signals are coupled to or from the SDRAM on each transition of the clock signal, i.e., on both the rising edge and the falling edge, the maximum data bandwidth can be achieved in the burst 4 mode by applying the bank/row address signals to the SDRAM on the first rising edge of the clock signal and the column address signals can be applied to the SDRAM on the next rising edge of the clock signal. Similar timing relationships between the address signals and the data signals exist for operations in other burst modes, such as the burst 2 or burst 8 mode.
The timing relationship between the address signals and the data signals vary as a function of the manner in which the address signals are coupled to the SDRAM. The address signals for a bank address, a row address and a column address may be coupled to the SDRAM at the same time by using an address bus having a larger number of address bits. The received address signals can them be multiplexed into bank address signals, row address signals and column address signals in the SDRAM. However, a very wide address bus is undesirable for a number of reasons. A narrower address bus is preferable, but a narrower address bus requires that the SDRAM process addresses at a faster speed for the same addressing rate.
The burst mode, as well as the number of data bits that will be coupled to or from the SDRAM with each burst, can be selected by appropriate command signals coupled to the SDRAM. However, the size of the address bus and the manner in which the addresses are applied to the SDRAM do not normally vary during operation of a system using the SDRAM. As a result, different SDRAM devices must be manufactured and sold to meet the requirements of customers using the SDRAM devices in electronic systems. It is relatively expensive to design and manufacture a wide variety of SDRAM devices having respective addressing configurations. It is also relatively expensive for venders of SDRAM devices to stock a wide variety of SDRAM devices having respective addressing configurations. As a result, the wide variety of SDRAM devices that are demanded by customers is a significant component of the price of SDRAM devices. Similar factors also increase the price of other types of memory devices, such as SRAM devices.
There is therefore a need for memory device and method that can be easily and quickly adapted to a wide variety of addressing configurations so that it is only necessary to manufacture and sell a single memory device to suit a wide variety of customer needs.